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74LVC573A octal d-type transparent latch with 5-volt tolerant inputs/outputs (3-state) product specification 1998 jul 29 integrated circuits
philips semiconductors product specification 74LVC573A octal d-type transparent latch with 5-volt tolerant inputs/outputs (3-state) 2 1998 jul 29 853-1862 19804 features ? 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic ? supply voltage range of 2.7v to 3.6v ? complies with jedec standard no. 8-1a ? inputs accept voltages up to 5.5v ? cmos low power consumption ? direct interface with ttl levels ? high impedance when v cc = 0v ? flow-through pin-out architecture description the 74LVC573A is a high-performance, low-power, low-voltage, si-gate cmos device, superior to most advanced cmos compatible ttl families. inputs can be driven from either 3.3v or 5v devices. in 3-state operation, outputs can handle 5v. this feature allows the use of these devices as translators in a mixed 3.3v/5v environment. the 74LVC573A is an octal d-type transparent latch featuring separate d-type inputs for each latch and 3-state outputs for bus-oriented applications. a latch enable (le) input and an output enable (oe ) input are common to all internal latches. the '573a' consists of eight d-type transparent latches with 3-state true outputs. when le is high, data at the d n inputs enters the latches. in this condition, the latches are transparent, i.e. a latch output will change each time its corresponding d-input changes. when le is low, the latches store the information that was present at the d-inputs one setup time preceding the high-to-low transition of le. when oe is low, the contents of the eight latches are available at the outputs. when oe is high, the outputs go to the high impedance off-state. operation of the oe input does not affect the state of the latches. the '573a' is functionally identical to the '373a', but the '373a' has a different pin arrangement. quick reference data symbol parameter conditions typical unit t phl /t plh propagation delay d n to q n; le to q n c l = 50pf v cc = 3.3v 4.3 4.6 ns c i input capacitance 5.0 pf c pd power dissipation capacitance per latch notes 1 and 2 20 pf note: 1. c pd is used to determine the dynamic power dissipation (p d in w): p d = c pd x v cc 2 x f i + (c l x v cc 2 x f o ) where: f i = input frequency in mhz; c l = output load capacity in pf; f o = output frequency in mhz; v cc = supply voltage in v; (c l x v cc 2 x f o ) = sum of outputs. 2. the condition is v i = gnd to v cc ordering information packages temperature range outside north america north america pkg. dwg. # 20-pin plastic shrink small outline (so) 40 c to +85 c 74LVC573A d 74LVC573A d sot163-1 20-pin plastic shrink small outline (ssop) type ii 40 c to +85 c 74LVC573A db 74LVC573A db sot339-1 20-pin plastic thin shrink small outline (tssop) type i 40 c to +85 c 74LVC573A pw 7lvc573apw dh sot360-1
philips semiconductors product specification 74LVC573A octal d-type transparent latch with 5-volt tolerant inputs/outputs (3-state) 1998 jul 29 3 pin description pin number symbol function 1 oe output enable input (active-low) 2, 3, 4, 5, 6, 7, 8, 9 d0-d7 data inputs 19, 18, 17, 16, 15, 14, 13, 12 q0-q7 data outputs 10 gnd ground (0v) 11 le latch enable input (active-high) 20 v cc positive supply voltage pin configuration 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 v cc q0 q1 q2 q3 q4 q5 q6 q7 le oe d0 d1 d2 d3 d4 d5 d6 d7 gnd sa00395 logic symbol 11 1 le oe 2 3 4 5 6 7 8 9 d0 d1 d2 d3 d4 d5 d6 d7 19 18 17 16 15 14 13 12 q0 q1 q2 q3 q4 q5 q6 q7 sa00396 logic symbol (ieee/iec) 1 2 19 3 18 4 17 5 16 c1 11 en1 6 15 7 14 8 13 9 12 1d sa00397 functional diagram 1 19 2 318 17 4 516 11 15 6 714 13 8 912 oe q0 d0 d1 q1 q2 d2 d3 q3 q4 d4 d5 q5 q6 d6 d7 q7 le latch 1 to 8 3-state outputs sa00398
philips semiconductors product specification 74LVC573A octal d-type transparent latch with 5-volt tolerant inputs/outputs (3-state) 1998 jul 29 4 logic diagram le q d d0 d d1 d d2 d d3 d d4 d d5 d d6 d d7 le le le le le le le le le le le le le le le le qqq qq qq sa00399 q0 q1 q2 q3 q4 q5 q6 q7 oe latch 1 latch 2 latch 3 latch 4 latch 5 latch 6 latch 7 latch 8 function table operating modes inputs internal latches outputs operating modes oe le d n internal latches q 0 to q 7 enable and read register (transparent mode) l l h h l h l h l h latch and read register l l l l l h l h l h latch register and disable outputs h h l l l h l h z z h = high voltage level h = high voltage level one setup time prior to the high-to-low le transition l = low voltage level l = low voltage level one setup time prior to the high-to-low le transition x = don't care z = high impedance off-state
philips semiconductors product specification 74LVC573A octal d-type transparent latch with 5-volt tolerant inputs/outputs (3-state) 1998 jul 29 5 recommended operating conditions symbol parameter conditions limits unit symbol parameter conditions min max unit v cc dc supply voltage (for max. speed performance) 2.7 3.6 v v cc dc supply voltage (for low-voltage applications) 1.2 3.6 v v i dc input voltage range 0 5.5 v v o dc output voltage range; output high or low state 0 v cc v o dc output voltage range; output 3-state 0 5.5 t amb operating ambient temperature range in free-air 40 +85 c t r , t f input rise and fall times v cc = 1.2 to 2.7v v cc = 2.7 to 3.6v 0 0 20 10 ns/v absolute maximum ratings 1 in accordance with the absolute maximum rating system (iec 134) voltages are referenced to gnd (ground = 0v) symbol parameter conditions rating unit v cc dc supply voltage 0.5 to +6.5 v i ik dc input diode current v i 0 50 ma v i dc input voltage note 2 0.5 to +6.5 v i ok dc output diode current v o v cc or v o 0 50 ma v o dc output voltage; output high or low state note 2 0.5 to v cc +0.5 v v o dc output voltage; output 3-state note 2 0.5 to 6.5 v i o dc output source or sink current v o = 0 to v cc 50 ma i gnd , i cc dc v cc or gnd current 100 ma t stg storage temperature range 65 to +150 c power dissipation per package p tot plastic mini-pack (so) above +70 c derate linearly with 8 mw/k 500 mw plastic shrink mini-pack (ssop and tssop) above +60 c derate linearly with 5.5 mw/k 500 mw notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the input and output voltage ratings may be exceeded if the input and output current ratings are observed.
philips semiconductors product specification 74LVC573A octal d-type transparent latch with 5-volt tolerant inputs/outputs (3-state) 1998 jul 29 6 dc electrical characteristics over recommended operating conditions voltages are referenced to gnd (ground = 0v) limits symbol parameter test conditions temp = -40 c to +85 c unit min typ 1 max v high level in p ut voltage v cc = 1.2v v cc v v ih high le v el inp u t v oltage v cc = 2.7 to 3.6v 2.0 v v low level in p ut voltage v cc = 1.2v gnd v v il low le v el inp u t v oltage v cc = 2.7 to 3.6v 0.8 v v cc = 2.7v; v i = v ih or v il ;i o = 12ma v cc 0.5 v o high level out p ut voltage v cc = 3.0v; v i = v ih or v il ;i o = 100 m a v cc 0.2 v cc v v oh high le v el o u tp u t v oltage v cc = 3.0v; v i = v ih or v il; i o = 18ma v cc 0.6 v v cc = 3.0v; v i = v ih or v il; i o = 24ma v cc 0.8 v cc = 2.7v; v i = v ih or v il ;i o = 12ma 0.40 v ol low level output voltage v cc = 3.0v; v i = v ih or v il ;i o = 100 m a gnd 0.20 v v cc = 3.0v; v i = v ih or v il; i o = 24ma 0.55 i in p ut leakage current 2 v cc =36v ; v = 5 5v or gnd 01 5 m a i i inp u t leakage c u rrent 2 v cc = 3 . 6v ; v i = 5 . 5v or gnd 0 . 1 5 m a i oz 3-state output off-state current v cc = 3.6v; v i = v ih or v il ;v o = 5.5v or gnd 0.1 10 m a i off power off leakage supply v cc = 0.0v; v i or v o = 5.5v 0.1 10 m a i cc quiescent supply current v cc = 3.6v; v i = v cc or gnd; i o = 0 0.1 10 m a d i cc additional quiescent supply current per input pin v cc = 2.7v to 3.6v; v i = v cc 0.6v; i o = 0 5 500 m a notes: 1. all typical values are at v cc = 3.3v and t amb = 25 c. 2. the specified overdrive current at the data input forces the data input to the opposite logic input state. ac characteristics gnd = 0v; t r = t f 2.5ns; c l = 50pf; r l = 500 w ; t amb = 40 c to +85 c. limits symbol parameter waveform v cc = 3.3v 0.3v v cc = 2.7v v cc = 1.2v unit min typ 1 max min max typ t phl t plh propagation delay d n to q n 1, 5 1.5 4.3 6.2 1.5 7.2 19 ns t phl t plh propagation delay le to q n 2, 5 1.5 4.6 6.5 1.5 7.5 21 ns t pzh t pzl 3-state output enable time oe to q n 2, 5 1.5 3.8 7.5 1.5 8.5 17 ns t phz t plz 3-state output disable time oe to q n 3, 5 1.5 3.5 6.0 1.5 6.5 15 ns t w le pulse width high 2 3.2 1.6 3.2 ns t su setup time d n to le 4 1.7 0.3 1.7 ns t h hold time d n to le 4 1.4 0.2 1.5 ns note: 1. unless otherwise stated, all typical values are at v cc = 3.3v and t amb = 25 c.
philips semiconductors product specification 74LVC573A octal d-type transparent latch with 5-volt tolerant inputs/outputs (3-state) 1998 jul 29 7 ac waveforms v m = 1.5v at v cc 2.7v; v m = 0.5 v cc at v cc 2.7v. v ol and v oh are the typical output voltage drop that occur with the output load. v x = v ol + 0.3v at v cc 2.7v; v x = v ol + 0.1 v cc at v cc 2.7v v y = v oh 0.3v at v cc 2.7v; v y = v oh 0.1 v cc at v cc 2.7v sy00041 input v m t phl t plh v ol v i v m gnd v oh output waveform 1. input (d n ) to output (qn) propagation delays. t w t phl t plh le input qn output v m v m sa00388 v i gnd v oh v ol waveform 2. latch enable input (le) pulse width, the latch enable input to output (q n ) propagation delays t plz t pzl v i noe input gnd v cc q n output low-to-off off-to-low v ol v oh q n output high-to-off off-to-high gnd outputs enabled outputs enabled outputs disabled t phz v m v m v m t pzh v x v y sw00207 waveform 3. 3-state enable and disable times. v m dn input v m le input t su th note: the shaded areas indicate when the input is permitted to change for predictable output performance. sw00073 t su th v i gnd v i gnd waveform 4. data setup and hold times for the d n input to the le input. test circuit pulse generator r t v in d.u.t. v out c l v cc r l =500 w switch position test switch t plh /t phl open t plz /t pzl 2 v cc t phz /t pzh gnd test circuit for 3-state outputs open gnd s 1 2 v cc definitions v cc 2.7v 2.7 3.6v v in v cc 2.7v r l = load resistor c l = load capacitance includes jig and probe capacitance r t = termination resistance should be equal to z out of pulse generators. sw00047 r l =500 w waveform 5. load circuitry for switching times.
philips semiconductors product specification 74LVC573A octal d-type transparent latch with 5-volt tolerant inputs/outputs (3-state) 1998 jul 29 8 so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1
philips semiconductors product specification 74LVC573A octal d-type transparent latch with 5-volt tolerant inputs/outputs (3-state) 1998 jul 29 9 ssop20: plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1
philips semiconductors product specification 74LVC573A octal d-type transparent latch with 5-volt tolerant inputs/outputs (3-state) 1998 jul 29 10 tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1
philips semiconductors product specification 74LVC573A octal d-type transparent latch with 5-volt tolerant inputs/outputs (3-state) 1998 jul 29 11 notes
philips semiconductors product specification 74LVC573A octal d-type transparent latch with 5-volt tolerant inputs/outputs (3-state) yyyy mmm dd 12 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. print code date of release: 08-98 document order number: 9397-750-04513
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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